- A process executes in its private virtual address space, composed of pages, each representing a contiguous range of addresses.
- The typical page size is 4KB.
- Each page is mapped to an arbitrary frame in physical memory.
In virtualized environments there are two levels of address-space virtualization.
1) the virtual addresses of a process -> guest’s notion of physical address, i.e., the VM’s emulated physical memory
2) guest physical addresses -> physical addresses of the processor
Translations from virtual pages to physical frames are stored in page tables.
Processor cache recently used page table entries in the translation look-aside-buffer (TLB).
The TLB is scarce processor resource with a small number of entries.
Large pages used the TLB more efficiently, since fewer entries are needed to map a particular region of memory. As a result, the performance of application with large memory footprint, such as Oracle database or high-performance computing applications, can benefit from using large pages.
For the same reason, VMMs, such as VMWare ESX and Xen HVM, also use large pages for mapping guest physical memory.
 Last-Level Cache Side-Channel Attacks are Practical, by Fangfei Liu et al, in Security&Privacy 2015